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#	Item
141	Ehcache v1.2.4 User Guide Greg Luck 26 November 2006 2 Add to Reading List Source URL: www.ehcache.org Language: English - Date: 2016-02-25 06:01:44 Computing Cache Java enterprise platform Software Ehcache Object-relational mapping Distributed cache CPU cache Hibernate
142	HyperThreading Considered Harmful Colin Percival Colin Percival Add to Reading List Source URL: www.daemonology.net Language: English - Date: 2006-05-14 06:23:45 Computing Cache Computer memory Computer architecture Computer engineering Cache memory Hyper-threading Pentium Xeon Thread CPU cache
143	Learning Models in Self-Optimizing Systems Karan Singh Vincent Weaver Cornell University Add to Reading List Source URL: web.eece.maine.edu Language: English - Date: 2007-04-09 13:35:18 Cybernetics Cache Computational neuroscience CPU cache Central processing unit Computer memory Artificial neural network FLOPS Genetic algorithm Machine learning Pentium III Benchmark
144	Performance of vSphere Flash Read Cache in VMware vSphere 5.5 Add to Reading List Source URL: www.vmware.com Language: English - Date: 2015-12-15 05:51:00 Computing Cache Computer hardware Software Computer memory CPU cache Central processing unit IOPS VMware vSphere Solid-state drive Oracle Database VMDK
145	A Component Model of Spatial Locality Xiaoming Gu Intel China Research Center Beijing, China Joint work with Ian Christoper, Add to Reading List Source URL: sysrun.haifa.il.ibm.com Language: English - Date: 2009-08-27 04:46:16 Cache Computer memory Computing Software optimization Locality of reference Computer engineering CPU cache Reuse
146	PDF Document Add to Reading List Source URL: amitlevy.com Language: English - Date: 2013-09-13 15:42:52 Computing Computer architecture Cache Computer memory Computer hardware Central processing unit Parallel computing CPU cache Scheduling Thread Monitor Context switch
147	Attacking SMM Memory via Intel® CPU Cache Poisoning Rafal Wojtczuk Joanna Rutkowska Add to Reading List Source URL: www.invisiblethingslab.com Language: English
148	Process scheduling • Goal: High throughput - Minimize context switches to avoid wasting CPU, TLB misses, cache misses, even page faults. • Goal: Low latency Add to Reading List Source URL: www.scs.stanford.edu Language: English - Date: 2006-10-17 14:15:16 Load Nice Context switch Thread Run queue CPU time Lottery scheduling Kernel Earliest deadline first scheduling Scheduling algorithms Computing Scheduling
149	Conﬂict Exceptions: Simplifying Concurrent Language Semantics with Precise Hardware Exceptions for Data-Races Brandon Lucia† Luis Ceze† Add to Reading List Source URL: homes.cs.washington.edu Language: English - Date: 2010-04-14 00:55:30 Arrays Computer architecture Cache coherency CPU cache Cache Central processing unit Parallel computing Lookup table Bit array Computing Computer memory Computer hardware
150	White paper QNAP Turbo NAS with SSD Cache 1 Add to Reading List Source URL: files1.qnap.com Language: English - Date: 2014-03-12 22:00:48 Computer performance Data transmission IOPS Solid-state drive CPU cache Smart Response Technology RAID VRPM Hybrid drive Computer hardware Computing Cache

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